LG 24MS53S-PZ - Manuale (Pagina 46)

IT
ALIANO
46
DIAGRAMMI A BLOCCHI
DIAGRAMMI A BLOCCHI
24MS53S_V24MS53S_V
EU
MTK EU
MTK
Block
Diagram
B
lo
ck
D
ia
gr
am
DDR3 1600
X
16
(512MB
X
2E
A)
X
TA
L
CI SlotCI Slot P_TS
P_TS
T/C
D
em
od
IF (+/-)
(512MB
X
2E
A)
800Mhz
An
alo
g
De
m
od
SY
ST
EM
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PR
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M
Air
/
Cable
TUNER (T/C/A
)
DDR3
1600
X
16
(256MB
X
1E
A)
667Mhz
X_
TA
L
27MHz
T/C
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2 W
ith
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TV
T/C
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2 W
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TV
A
B
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alo
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D
em
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ST
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EE
PR
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(2
56
K
b)
(
)
TUNER
(S2)
DVB-S
DEMOD
(S2)
USB2
eM
M
C
(4
G
B
)
P_TS
HDCP EEPROM
(1
6K
b)
U
SB P_TS
I2C
5 I2C
1
Tu
ne
r :
I2
C
6
DVB-S : I2C
4
O
C
P
2.5
A O
C
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1A
(H
D
D
)
R E A R
E A R (H
)
Audio
AMP
M
TK
A
2
HDMI1 HDMI2
HDMI M
U
X
LN
B
30P
(4
G
B
)
50P 50P
I2S
Out
EP
I (N
/A
)
I2C
2 LVDS
M
H
L 1
A
SIL1392
M
H
L :
I2
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4
M
H
L c
on
ne
ct
PM
IC
(N
/A
)
LE
VE
L
SH
IF
TE
R
(N
/A
)
R E A R
Au
dio
AM
P
(NTP7513)
I2C
1
H/P
AV
/C
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M
P
R E
AM
P
TI
C
VB
S/Y
Pb
Pr
LO
C
AL
D
IM
M
IN
G
(N
/A
)
B
LU
TO
O
TH
I2C
1 UA
RT
IR
SC
ART
CVBS/RGB
LA
N
#EPI
&
LVDS
Diagram
A R
ETHERNET
IR /
NFC
W
IF
I
K
EY
LO
G
O
L
IG
H
T
(N
/A
)
SU
B
AS
SY
IR
K
EY
USB_WIFI
Su
b M
ic
om
(R
EN
ES
A
S R
5F
10
00
G
)
X_T
AL
I2C
3
32.76
8KHz
24MS53V 24MS53S